The disclosed subject matter relates generally to semiconductor device manufacturing and, more particularly, to a cell array with density features and a method for instantiating the cell array.
Integrated circuit devices are typically designed using a combination of automated design techniques and manual design techniques. One type of structure commonly designed using an automated design technique is a parameterized cell (pcell). Parameterized cells are generally laid out using an array structure, as illustrated in FIG. 1. An array 100 includes a plurality of unit cells 110 grouped into sub-arrays 120, each having n×m unit cells 110. Sub-arrays 120 are then replicated in a row 130 and column 140 arrangement. The total number of unit cells 110 in the array 100 is i×j. In some structures, certain parameters of each cell 110, such as resistance, structure length, structure width, etc. may vary across the array 100, while in others, the cell parameters may be fixed.
Conventionally, unit cells are instantiated into closely-packed sub-arrays and arrays to minimize overall array size. In such designs, a component in a certain design layer of a unit cell can exclude other components in different design layers from being placed in its proximity. One example is a poly-silicon (PC) shape in a poly-resistor (PR) cell that excludes diffusion (RX). This restriction can consistently block components in a certain design layer and create a continuous keep-out zone for the design layer throughout the array. This arrangement may result in yield loss, because stringent layout pattern uniformity is required for several key design layers. The large keep-out zone can result in a violation of the pattern uniformity requirement. In the example of a poly resistor array, a large void of diffusion in the array can cause a diffusion minimum density rule violation. On the other side of the density rule spectrum, a unit cell with a design component that occupies a large fraction of the cell area can result in a maximum density rule violation when instantiated as an array.
Many times designers only find these maximum and minimum density rule violations at a very late stage in the design cycle when pattern uniformity is checked by a design rule checker (DRC). The need to rearrange the cell arrays to address a density issue at such a late stage is a frequent reason for a delay in completing a design.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.